PSD833F2 datasheet(96/110 Pages) STMICROELECTRONICS

96 / 110 page

PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2

96/110

Table 64. Port A Peripheral Data Mode WRITE Timing (3V devices)

Note: 1. RD has the same timing as DS, LDS, UDS, and PSEN (in 8031 combined mode).

2. WR has the same timing as the E, LDS, UDS, WRL, and WRH signals.

3. Any input used to select Port A Data Peripheral mode.

4. Data is already stable on Port A.

5. Data stable on ADIO pins to data on Port A.

Figure 49. Reset (RESET) Timing

Table 65. Reset (RESET) Timing (5V devices)

Note: 1. Reset (RESET) does not reset Flash memory Program or Erase cycles.

2. Warm reset aborts Flash memory Program or Erase cycles, and puts the device in READ Mode.

Table 66. Reset (RESET) Timing (3V devices)

Note: 1. Reset (RESET) does not reset Flash memory Program or Erase cycles.

2. Warm reset aborts Flash memory Program or Erase cycles, and puts the device in READ Mode.

Symbol

Parameter

Conditions

-12

-15

-20

Unit

Min

Max

Min

Max

Min

Max

tWLQV–PA

WR to Data Propagation Delay

(Note 2)

tDVQV–PA

Data to Port A Data Propagation Delay

(Note 5)

tWHQZ–PA

WR Invalid to Port A Tri-state

(Note 2)

Symbol

Parameter

Conditions

Min

Max

Unit

tNLNH

RESET Active Low Time 1

150

tNLNH–PO

Power On Reset Active Low Time

tNLNH–A

Warm Reset (on the PSD834Fx) 2

µs

tOPR

RESET High to Operational Device

120

Symbol

Parameter

Conditions

Min

Max

Unit

tNLNH

RESET Active Low Time 1

300

tNLNH–PO

Power On Reset Active Low Time

tNLNH–A

Warm Reset (on the PSD834Fx) 2

µs

tOPR

RESET High to Operational Device

300

tNLNH-PO

tOPR

AI02866b

RESET

tNLNH

tNLNH-A

tOPR

VCC

CC(min)

Power-On Reset

Warm Reset

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