PSD833F2 datasheet(68/110 Pages) STMICROELECTRONICS

No de pièce	PSD833F2

Description	Flash In-System Programmable (ISP) Peripherals for 8-bit MCUs, 5V

PDF	110 Pages

Scroll/Zoom	100%

Fabricant	STMICROELECTRONICS [STMicroelectronics]

Site Internet	http://www.st.com

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68 / 110 page

PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2

68/110

Table 33. Status During Power-On Reset, Warm Reset and Power-down Mode

Note: 1. The SR_cod and PeriphMode bits in the VM Register are always cleared to '0' on Power-On Reset or Warm Reset.

Port Configuration

Power-On Reset

Warm Reset

Power-down Mode

MCU I/O

Input mode

Unchanged

PLD Output

Valid after internal PSD

configuration bits are

loaded

Valid

Depends on inputs to PLD

(addresses are blocked in

PD mode)

Address Out

Tri-stated

Not defined

Data Port

Tri-stated

Peripheral I/O

Tri-stated

Power-On Reset

Warm Reset

Power-down Mode

PMMR0 and PMMR2

Cleared to '0'

Unchanged

Macrocells flip-flop status

Cleared to '0' by internal

Power-On Reset

Depends on .re and .pr

equations

Depends on .re and .pr

equations

VM Register1

Initialized, based on the

selection in PSDsoft

Configuration menu

Initialized, based on the

selection in PSDsoft

Configuration menu

Unchanged

All other registers

Cleared to '0'

Unchanged

PSD833F2 Fiches technique(PDF) 68 Page - STMicroelectronics

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