DSP56166ROM datasheet(41/63 Pages) MOTOROLA

41 / 63 page

PRELIMINARY - 6/15/93

DSP56166 Technical Data Sheet

MOTOROLA

AC Electrical Characteristics — Bus Arbitration Timing — Master Mode

VCC = 5.0 Vdc +/- 10%, TJ = -40 to +125˚ C, CL = 50 pF + 1 TTL Load.

NOTES:

1. With no external access from the DSP56166

2. During external read or write access

3. During external read-modify-write access

4. During STOP mode — external bus is released and BG is always low

5. During WAIT mode

Num

Characteristic

60MHz

Unit

Min

Max

CLKO high to BR Output Valid

7.3

BG Input Valid to CLKO Low (Setup)

1.7

—

CLKO Low to BG Input Deassertion

(Hold)

TBD

—

BB Input Deassertion to CLKO Low

(Setup)

1.5

—

CLKO Low to BB Input Deassertion

(Hold)

TBD

—

CLKO High to BB Output Assertion

8.0

CLKO Low to BG Input Assertion

(See note 1)

(See note 2)

TBD

—

BG Deassertion

to BB Deassertion

(See note 1)

(See note 2)

(See note 3)

(See note 4)

(See note 5)

TBD

BG Deassertion to

Addr/Data/Control

(See note 1)

Three-state

(See note 2)

(See note 3)

(See note 4)

(See note 5)

TBD

DSP56166ROM Fiches technique(PDF) 41 Page - Motorola, Inc

DSP56166ROM Fiches technique(HTML) 41 Page - Motorola, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63

Fiches technique Télécharger

Lien URL