AD9856SLASHPCB datasheet(24/37 Pages) AD

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AD9856

Rev. C | Page 23 of 36

–150

–120

–90

–60

–30

020

DISPLAYED FREQUENCY IS RELATIVE TO I/Q NYQ. BW

–4.0

–3.5

–3.0

–2.5

–2.0

–1.5

–1.0

–0.5

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

DISPLAYED FREQUENCY IS RELATIVE TO I/Q NYQ. BW

Figure 39. CIC Filter Frequency Response (R = 2, HBF 3 Selected)

Figure 40. Pass-Band Detail (R = 2, HBF 3 Selected)

–150

–120

–90

–60

–30

144

288

432

576

720

864

1008

DISPLAYED FREQUENCY IS RELATIVE TO I/Q NYQ. BW

–4.0

–3.5

–3.0

–2.5

–2.0

–1.5

–1.0

–0.5

0.2

0.4

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0.8

1.0

1.2

1.4

1.6

1.8

2.0

DISPLAYED FREQUENCY IS RELATIVE TO I/Q NYQ. BW

Figure 41. CIC Filter Frequency Response (R = 63, HBF 3 Active)

Figure 42. Pass-Band Detail (R = 63, HBF 3 Active)

DIGITAL QUADRATURE MODULATOR

Following the CIC filter stage the I and Q data (which have

been processed independently up to this point) are mixed in the

modulator stage to produce a digital modulated carrier. The

carrier frequency is selected by programming the direct digital

synthesizer (see the Direct Digital Synthesizer Function section)

with the appropriate 32-bit tuning word via the AD9856 control

registers. The DDS simultaneously generates a digital (sampled)

sine and cosine wave at the programmed carrier frequency. The

digital sine and cosine data is multiplied by the Q and I data,

respectively, to create the quadrature components of the

original data upconverted to the carrier frequency. The

quadrature components are digitally summed and passed on to

the subsequent stages.

The key point is that the modulation is done digitally, which

eliminates the phase and gain imbalance and crosstalk issues

typically associated with analog modulators. Note that the

modulated signal is actually a number stream sampled at the

rate of SYSCLK, which is the same rate at which the DAC is

clocked (see Figure 23).

Note that the architecture of the quadrature modulator results

in a 3 dB loss of signal level. To visualize this, assume that both

the I data and Q data are fixed at the maximum possible digital

value, x. Then the output of the modulator, y, is:

y = x × cos(ω) + x × sin(ω) = x × [cos(ω) + sin(ω)]

From this equation, y assumes a maximum value of x√2

(a gain of 3 dB). However, if the same number of bits were

used to represent the y values, as is used to represent the x

values, an overflow would occur. To prevent this, an effective

divide-by-two is implemented on the y values, which reduces

the maximum value of y by a factor of two. Because division by

two results in a 6 dB loss, the modulator yields an overall loss of

3 dB (3 dB − 6 dB = −3 dB, or 3 dB of loss).

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