TLE4471 datasheet(19/26 Pages) INFINEON

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Data Sheet Rev. 1.1

2001-09-06

TLE 4471

The reset delay time

dr is defined by the reset delay capacitor CDR at pin DR and can be

calculated as follows:

With

reset delay capacitor

reset delay time required by the application

DR, dt typical 1.8 V for power up reset

DR, ch charge current typical 4 µA

For a delay capacitor

DR = 100 nF the typical power up reset delay time is 45 ms.

The under-voltage reset circuitry supervises the output voltage. In case

Q1 falls below

the reset threshold the reset output is set LOW after the reset reaction time

rr (discharge

of the reset delay capacitor). The reset LOW signal is held down to an output voltage

of 1 V. Both, the reset reaction time and the reset delay time are defined by the capacitor

value.

The reset reaction time

rr is the time it takes the voltage regulator to set its reset output

LOW after the output voltage has dropped below the reset threshold. The reset reaction

time can be calculated using the following equation:

tdr CDR

VDR dt

IDR ch

----------------

⋅

trr CDR

VDR dt

VDR st

–

IDR dis

--------------------------------------

⋅

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