STHDLS101A datasheet(8/24 Pages) STMICROELECTRONICS

8 / 24 page

Pin configuration

STHDLS101A

8/24

Doc ID 15756 Rev 1

SCL_SOURCE

Input

3.3 V DDC clock I/O. Pulled-up by external termination

to 3.3 V. Connected to SCL_SINK through voltage-

limiting integrated NMOS pass-gate

ANALOG2

Analog

Analog connection determined by vendor. Acceptable

connections to this pin are:

– Resistor or capacitor to GND

– Resistor or capacitor to 3.3 V

– Short to 3.3 V or to GND

–NC

VCC33

Power

3.3 V ±10% DC supply

GND

Power

Ground

OUT_D4+

Output

HDMI 1.3 compliant TMDS output

OUT_D4+ makes a differential output signal with

OUT_D4-

Output

HDMI 1.3 compliant TMDS output

OUT_D4- makes a differential output signal with

OUT_D4+

VCC33

Power

3.3 V±10% DC supply

OUT_D3+

Output

HDMI 1.3 compliant TMDS output

OUT_D3+ makes a differential output signal with

OUT_D3-

Output

HDMI 1.3 compliant TMDS output

OUT_D3- makes a differential output signal with

OUT_D3+.

GND

Power

Ground

OUT_D2+

Output

HDMI 1.3 compliant TMDS output

OUT_D2+ makes a differential output signal with

OUT_D2-.

OUT_D2-

Output

HDMI 1.3 compliant TMDS output

OUT_D2- makes a differential output signal with

OUT_D2+

VCC33

Power

3.3 V±10% DC supply

OUT_D1+

Output

HDMI 1.3 compliant TMDS output. OUT_D1+ makes a

differential output signal with OUT_D1-

OUT_D1-

Output

HDMI 1.3 compliant TMDS output. OUT_D1- makes a

differential output signal with OUT_D1+

GND

Power

Ground

Table 2.

Pin description (continued)

number

Name

Type

Function

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