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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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STM8S007C8 Fiches technique(PDF) 71 Page - STMicroelectronics |
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STM8S007C8 Fiches technique(HTML) 71 Page - STMicroelectronics |
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71 / 92 page  DocID022171 Rev 5 71/92 STM8S007C8 Electrical characteristics 82 Figure 30. Typical NRST pull-up resistance vs VDD @ 3 temperatures Figure 31. Typical NRST pull-up current vs VDD @ 3 temperatures The reset network shown in Figure 32 protects the device against parasitic resets. The user must ensure that the level on the NRST pin can go below the VIL max. level specified in Table 35. Otherwise the reset is not taken into account internally. For power consumption sensitive applications, the capacity of the external reset capacitor can be reduced to limit charge/discharge current. If the NRST signal is used to reset the external circuitry, care must be taken of the charge/discharge time of the external capacitor to fulfill the external device’s reset timing conditions. The minimum recommended capacity is 10 nF. |
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