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ST72321R7-Auto Fiches technique(PDF) 45 Page - STMicroelectronics

No de pièce ST72321R7-Auto
Description  PLL for 2x frequency multiplication
PDF  243 Pages
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Fabricant  STMICROELECTRONICS [STMicroelectronics]
Site Internet  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

ST72321R7-Auto Fiches technique(HTML) 45 Page - STMicroelectronics

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ST72321xx-Auto
Supply, reset and clock management
Doc ID 13829 Rev 1
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Figure 15.
Using the AVD to monitor VDD (AVDS bit = 0)
Monitoring a voltage on the EVD pin
This mode is selected by setting the AVDS bit in the SICSR register.
The AVD circuitry can generate an interrupt when the AVDIE bit of the SICSR register is set.
This interrupt is generated on the rising and falling edges of the comparator output. This
means it is generated when either one of these two events occur:
●
VEVD rises up to VIT+(EVD)
●
VEVD falls down to VIT-(EVD)
The EVD function is illustrated in Figure 16.
For more details, refer to Section 19: Electrical characteristics.
VDD
VIT+(AVD)
VIT-(AVD)
AVDF bit
0
0
RESET VALUE
IF AVDIE bit = 1
Vhyst
AVD INTERRUPT
REQUEST
INTERRUPT PROCESS
INTERRUPT PROCESS
VIT+(LVD)
VIT-(LVD)
LVD RESET
Early Warning Interrupt
(Power has dropped, MCU not
not yet in reset)
1
1
trv VOLTAGE RISE TIME



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