ST7262XXX datasheet(51/139 Pages) STMICROELECTRONICS

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ST7262xxx

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Doc ID 6996 Rev 5

PWM AUTO-RELOAD TIMER (Cont’d)

INPUT CAPTURE

CONTROL / STATUS REGISTER (ARTICCSR)

Read/Write (except bits 1:0 read and clear)

Reset Value: 0000 0000 (00h)

Bit 7:6 = Reserved, always read as 0.

Bit 5:4 = CS[2:1] Capture Sensitivity

These bits are set and cleared by software. They

determine the trigger event polarity on the corre-

sponding input capture channel.

0: Falling edge triggers capture on channel x.

1: Rising edge triggers capture on channel x.

Bit 3:2 = CIE[2:1] Capture Interrupt Enable

These bits are set and cleared by software. They

enable or disable the Input capture channel inter-

rupts independently.

0: Input capture channel x interrupt disabled.

1: Input capture channel x interrupt enabled.

Bit 1:0 = CF[2:1] Capture Flag

These bits are set by hardware when a capture oc-

curs and cleared by hardware when software

reads the ARTICCSR register. Each CFx bit indi-

cates that an input capture x has occurred.

0: No input capture on channel x.

1: An input capture has occurred on channel x.

INPUT CAPTURE REGISTERS (ARTICRx)

Read only

Reset Value: 0000 0000 (00h)

Bit 7:0 = IC[7:0] Input Capture Data

These read only bits are set and cleared by hard-

ware. An ARTICRx register contains the 8-bit

auto-reload counter value transferred by the input

capture channel x event.

CS2

CS1

CIE2

CIE1

CF2

CF1

IC7

IC6

IC5

IC4

IC3

IC2

IC1

IC0

Obsolete

Product(s)

- Obsolete

Product(s)

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