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TNETV2501INPGF Fiches technique(PDF) 66 Page - Texas Instruments |
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TNETV2501INPGF Fiches technique(HTML) 66 Page - Texas Instruments |
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66 / 197 page ![]() Functional Overview 66 December 2002 − Revised November 2008 SPRS206K 3.9.5 PLL Control Registers The 5501 PLL control registers are accessible via the I/O memory map. Table 3−11. PLL Control Registers ADDRESS REGISTER ADDRESS REGISTER 1C80h PLLCSR 1C82h CK3SEL 1C88h PLLM 1C8Ah PLLDIV0 1C8Ch PLLDIV1 1C8Eh PLLDIV2 1C90h PLLDIV3 1C92h OSCDIV1 1C98h WKEN 8400h CLKOUTSR 8C00h CLKMD 3.9.5.1 PLL Control / Status Register (PLLCSR) 15 8 Reserved R, 00000000 76 54 32 10 Reserved STABLE LOCK Reserved PLLRST OSCPWRDN PLLPWRDN PLLEN R, 0 R, 1 R, 0 R, 0 R/W, 1 R/W, 0 R/W, 0 R/W, 0 LEGEND: R = Read, W = Write, n = value at reset Figure 3−15. PLL Control/Status Register Layout (0x1C80) |
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