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STBC02BJR Fiches technique(PDF) 9 Page - STMicroelectronics |
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STBC02BJR Fiches technique(HTML) 9 Page - STMicroelectronics |
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9 / 39 page ![]() STBC02 Pin configuration (top through view) DocID029261 Rev 2 9/39 Bump Bump name Description Digital I/Os nRESET C2 Smart reset output signal (open drain output). A pull-up resistor (10 – 100 kΩ) is connected to LDO pin or to a higher voltage RST_PENDING B2 Reset output signal (totem pole output) RESET_NOW A1 Smart reset input signal (referred to LDO level); RESET_CLEAR when watchdog is enabled Switch matrix SW1_I F3 Load switch SPDT1 input (1.8 V to 5 V range) If SPDT switches are used, decoupling capacitors are recommended on input and output. Capacitor values depend on application conditions and requirements. If not used, connect inputs and outputs to GND SW1_OA E4 Load switch SPDT1 output A (enabled/disabled by SWIRE) SW1_OB E3 Load switch SPDT1 output B (enabled/disabled by SWIRE) SW2_I E2 Load switch SPDT2 input (1.8 V to 5 V range) SW2_OA F2 Load switch SPDT2 output A (enabled/disabled by SWIRE) SW2_OB F1 Load switch SPDT2 output B (enabled/disabled by SWIRE) NC C3-D3 Not connected Leave floating |
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