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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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NSC800 Fiches technique(PDF) 10 Page - National Semiconductor (TI) |
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NSC800 Fiches technique(HTML) 10 Page - National Semiconductor (TI) |
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10 / 76 page  80 Functional Description This section reviews the CPU architecture shown below fo- cusing on the functional aspects from a hardware perspec- tive including timing details As illustrated in Figure 1 the NSC800 is an 8-bit parallel device The major functional blocks are the ALU register array interrupt control timing and control logic These areas are connected via the 8-bit internal data bus Detailed de- scriptions of these blocks ae provided in the following sec- tions TLC5171 – 9 Note Applicable pinout for 40-pin dual-in-line package within parentheses FIGURE 1 NSC800 CPU Functional Block Diagram 10 |
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