WM8521 datasheet(8/20 Pages) WOLFSON

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WM8521

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PP Rev 1.3 December 2004

MASTER CLOCK TIMING

MCLK

MCLKL

MCLKH

MCLKY

Figure 1 Master Clock Timing Requirements

Test Conditions

AVDD = 12V, DVDD = 3.3V, AGND / DGND = 0V, TA = +25

oC, fs = 48kHz, MCLK = 256fs unless otherwise stated.

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNIT

System Clock Timing Information

MCLK Master clock pulse width

high

tMCLKH

MCLK Master clock pulse width

low

tMCLKL

MCLK Master clock cycle time

tMCLKY

MCLK Duty cycle

40:60

60:40

Time from MCLK stopping to

digital reset

1.5

µs

DIGITAL AUDIO INTERFACE

Figure 2 Digital Audio Data Timing

Test Conditions

AVDD = 12V, DVDD = 3.3V, AGND / DGND = 0V, TA = +25

oC, fs = 48kHz, MCLK = 256fs unless otherwise stated.

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Audio Data Input Timing Information

BCLK cycle time

tBCY

BCLK pulse width high

tBCH

BCLK pulse width low

tBCL

LRCLK set-up time to BCLK

rising edge

tLRSU

LRCLK hold time from

BCLK rising edge

tLRH

DIN set-up time to BCLK

rising edge

tDS

DIN hold time from BCLK

rising edge

tDH

BCLK

LRCLK

BCH

BCL

BCY

DIN

LRSU

LRH

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