| Moteur de recherche de fiches techniques de composants électroniques |
|
WM9713 Fiches technique(PDF) 22 Page - Wolfson Microelectronics plc |
|
|
|||||||||||||||||||||||||||||
WM9713 Fiches technique(HTML) 22 Page - Wolfson Microelectronics plc |
|
22 / 111 page ![]() WM9713L Preliminary Technical Data 1 PTD, March 2004, Rev 2.2 22 Powerdown for the PLL and internal clocks is via registers 26h and 3Ch (see Table 6). REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 26h 13 PR5 1 (Off) Internal clock disable (active high) 3Ch 9 PLL 1 (Off) PLL powerdown (active high) N.B. both PR5 and PLL must be asserted low before PLL is enabled Table 6 PLL Powerdown Control DATA AND CONTROL INTERFACE The WM9713L has two interfaces, a data and control AC’97 interface and a data only PCM interface. The AC’97 interface is available through dedicated pins (SDATAOUT, SDATAIN, SYNC, BITCLK and RESETB) and is the sole control interface with access to all data streams on the device except for the Voice DAC. The PCM interface is available through the GPIO pins (PCMCLK, PCMFS, PCMDAC and PCMADC) and provides access to the Voice DAC. It can also transmit the data from the Stereo ADC. This can be useful, for example, to allow both sides of a phone conversation to be recorded by mixing the transmit and receive paths on one of the ADC channels and transmitting it over the PCM interface. AC97 INTERFACE INTERFACE PROTOCOL The WM9713Lhas a single AC’97 interface for both data transfer and control. The AC-Link uses 5 wires: • SDATAIN (pin 8) carries data from the WM9713L to the controller • SDATAOUT (pin 5) carries data from the controller to the WM9713L • BITCLK (pin 6) is a clock, derived from either MCLKA or MCLKB inputs and supplied to the controller. • SYNC is a synchronization signal generated by the controller and passed to the WM9713L • RESETB resets the WM9713L to its default state Figure 4 AC-Link Interface (typical case with BITCLK generated by the AC97 codec) The SDATAIN and SDATAOUT signals each carry 13 time-division multiplexed data streams (slots 0 to 12). A complete sequence of slots 0 to 12 is referred to as an AC-Link frame, and contains a total of 256 bits. The frame rate is 48kHz. This makes it possible to simultaneously transmit and receive multiple data streams (e.g. audio, touchpanel, AUXDAC, control) at sample rates up to 48kHz. Detailed information can be found in the AC’97 (Revision 2.2) specification, which can be obtained at www.intel.com/labs/media/audio/ |
|
Lien URL |
| ALLDATASHEET vous a-t-il été utile ? [ DONATE ] |
À propos de Alldatasheet | Publicité | Contactez-nous | Politique de confidentialité | Lien vers la fiche technique | Echange de liens | Fabricants All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |