HMC1197LP7FE datasheet(34/57 Pages) AD

34 / 57 page

For price, delivery, and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824

Phone: 978-250-3343

Fax: 978-250-3373

Order On-line at www.hittite.com

Application Support: Phone: 978-250-3343 or apps@hittite.com

HMC1197LP7FE

v03.0314

Wideband direct Quadrature Modulator

w/ Fractional-n Pll & Vco, 100 - 4000 MHz

1.7

chip identification

The chip id information may be read by reading the content of read only register, chip_ID in Reg 00h.

For HMC1197LP7FE, chip id is C7701Ah.

1.8

Serial Port overview

The SPI protocol has the following general features:

a. 3-bit chip address , enable the use of up to 8 devices connected to the serial bus

b. Simultaneous Write/Read during the SPI cycle

c. 5-bit address space

d. 3 wire for Write Only capability, 4 wire for Read/Write capability

Typical serial port operation can be run with SCLK at speeds up to 50 MHz.

1.8.1

Serial Port Write operation

AVDD = DVDD = 3V, AGND = DGND = 0V

table 13. SPi Write timing characteristics

Parameter

Conditions

Min.

Typ.

Max

Units

SDI setup time to SCLK Rising Edge

SCLK Rising Edge to SDI hold time

SEN low duration

SEN high duration

SCLK 32 Rising Edge to SEN Rising Edge

Recovery Time

Max Serial port Clock Speed

MHz

A typical WRITE cycle is shown in Figure 41.

a. The Master (host) places 24-bit data, d23:d0, MSB first, on SDI on the first 24 falling edges of SCLK.

b. the slave (HMC1197LP7FE) shifts in data on SDI on the first 24 rising edges of SCLK

c. Master places 5-bit register address to be written to, r4:r0, MSB first, on the next 5 falling edges of SCLK

(25-29)

d. Slave shifts the register bits on the next 5 rising edges of SCLK (25-29).

e. Master places 3-bit chip address, a2:a0, MSB first, on the next 3 falling edges of SCLK (30-32). Hittite

reserves chip address a2:a0 = 000 for HMC1197LP7FE.

f. Slave shifts the chip address bits on the next 3 rising edges of SCLK (30-32).

g. Master asserts SEN after the 32nd rising edge of SCLK.

h. Slave registers the SDI data on the rising edge of SEN.

i. Master clears SEN to complete the WRITE cycle.

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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

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For price, delivery, and to place orders: Analog Devices, Inc.,

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106

Phone: 781-329-4700 • Order online at www.analog.com

Application Support: Phone: 1-800-ANALOG-D

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