SI596 datasheet(4/12 Pages) SILABS

4 / 12 page

Si596

Rev. 1.0

Table 5. CLK± Output Phase Jitter

Parameter

Symbol

Test Condition

Min

Typ

Max

Units

Phase Jitter (RMS)1,2

for FOUT of 50 MHz < FOUT

810 MHz



Kv = 45 ppm/V

12 kHz to 20 MHz

—

0.5

—

Kv = 95 ppm/V

12 kHz to 20 MHz

—

0.5

—

Kv = 125 ppm/V

12 kHz to 20 MHz

—

0.5

—

Kv = 185 ppm/V

12 kHz to 20 MHz

—

0.5

—

Kv = 380 ppm/V

12 kHz to 20 MHz

—

0.7

—

Notes:

1. Refer to AN256 for further information.

2. For best jitter and phase noise performance, always choose the smallest KV that meets the application’s minimum APR

requirements. See “AN266: VCXO Tuning Slope (KV), Stability, and Absolute Pull Range (APR)” for more information.

Table 6. CLK± Output Period Jitter

Parameter

Symbol

Test Condition

Min

Typ

Max

Units

Period Jitter*

JPER

RMS

—

Peak-to-Peak

—

*Note: Any output mode, including CMOS, LVPECL, LVDS, CML. N = 1000 cycles. Refer to AN279 for further information.

Table 7. CLK± Output Phase Noise (Typical)

Offset Frequency

74.25 MHz

185 ppm/V

LVPECL

148.5 MHz

185 ppm/V

LVPECL

155.52 MHz

95 ppm/V

LVPECL

Units

100 Hz

1kHz

10 kHz

100 kHz

1MHz

10 MHz

20 MHz

–77

–101

–121

–134

–149

–151

–150

–68

–95

–116

–128

–144

–147

–148

–77

–101

–119

–127

–144

–147

–148

dBc/Hz

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