SI596 datasheet(3/12 Pages) SILABS

3 / 12 page

Si596

Rev. 1.0

Table 3. CLK± Output Frequency Characteristics

Parameter

Symbol

Test Condition

Min

Typ

Max

Units

Nominal Frequency1,2,3

LVDS/CML/LVPECL

—

810

MHz

CMOS

—

160

Temperature Stability1,4

TA = –40 to +85 ºC

–20

–50

—

+20

+50

ppm

Absolute Pull Range1,4

APR

±10

—

±370

ppm

Power up Time5

tOSC

——

Settling Time After FS Change

TFRQ

——

Notes:

1. See Section 3. "Ordering Information" on page 7 for further details.

2. Specified at time of order by part number.

3. Nominal output frequency set by VCNOM =VDD/2.

4. Selectable parameter specified by part number.

5. Time from power up or tristate mode to fO.

Table 4. CLK± Output Levels and Symmetry

Parameter

Symbol

Test Condition

Min

Typ

Max

Units

LVPECL Output Option1

mid-level

VDD – 1.42

—

VDD – 1.25

VOD

swing (diff)

1.1

—

1.9

VPP

VSE

swing (single-ended)

0.55

—

0.95

VPP

LVDS Output Option2

mid-level

1.125

1.20

1.275

VOD

swing (diff)

0.5

0.7

0.9

VPP

CML Output Option2

2.5/3.3 V option mid-level

—

VDD – 1.30

—

1.8 V option mid-level

—

VDD – 0.36

—

VOD

2.5/3.3 V option swing (diff)

1.10

1.50

1.90

VPP

1.8 V option swing (diff)

0.35

0.425

0.50

CMOS Output Option3

VOH

0.8 x VDD

—

VDD

VOL

——

0.4

Rise/Fall time (20/80%)

tR, tF

LVPECL/LVDS/CML

—

350

CMOS with CL =15pF

—

Symmetry (duty cycle)

SYM

LVPECL:

VDD – 1.3 V (diff)

LVDS:

1.25 V (diff)

CMOS:

VDD/2

—

Notes:

1. 50

 to V

DD – 2.0 V.

2. Rterm = 100  (differential).

3. CL = 15 pF. Sinking or sourcing 12 mA for VDD = 3.3V, 6mA for VDD = 2.5V, 3mA for VDD = 1.8 V.

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