ADL5205ACPZ-R7 datasheet(16/32 Pages) AD

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Data Sheet

ADL5205

Rev. 0 | Page 15 of 31

CH2 500mV/div 50Ω BW:8.0G

CH3 300mV/div 50Ω BW:5.0G

20.0ns/div

6.25GS/s

160ps/pt

A CH2

1.57V

Figure 42. Enable Time Domain Response at VPOS = 3.3 V

CH2 500mV/div 50Ω BW:8.0G

CH3 300mV/div 50Ω BW:5.0G

40.0ns/div

25.0GS/s

40.0ps/pt

A CH2

1.53V

Figure 43. Fast Attack Step Time Domain Response at VPOS = 5 V

CH2 500mV/div 50Ω BW:8.0G

CH3 300mV/div 50Ω BW:5.0G

20.0ns/div

25.0GS/s

40.0ps/pt

A CH2

1.53V

Figure 44. Fast Attack Step Time Domain Response at VPOS = 3.3 V

100

FREQUENCY (MHz)

CMRR 5V

CMRR 3.3V

Figure 45. CMRR vs. Frequency at Maximum Gain

250

200

1.0

1.2

1.4

1.6

1.8

2.0

2.2

2.4

2.6

2.8

150

VCMA OR VCMB (V)

100

3.3V

SETTLING TO WITHIN 1 dB,

FOR GAIN STEP FROM −9dB TO 26dB

Figure 46. Maximum Gain Transition Settling Time vs. Output Common-

Mode Voltage (VCMA or VCMB)

800

850

900

950

1000

100

1000

FREQUENCY (MHz)

3.3V, PM = 0

3.3V, PM = 1

5V, PM = 0

5V, PM = 1

Figure 47. Group Delay at Maximum Gain vs. Frequency over VPOS and Power

Modes

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