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T89C5115-RATIM Fiches technique(PDF) 52 Page - ATMEL Corporation |
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T89C5115-RATIM Fiches technique(HTML) 52 Page - ATMEL Corporation |
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52 / 105 page ![]() 52 T89C5115 4128A–8051–04/02 Interrupt Each Timer handles one interrupt source that is the timer overflow flag TF0 or TF1. This flag is set every time an overflow occurs. Flags are cleared when vectoring to the Timer interrupt routine. Interrupts are enabled by setting ETx bit in IEN0 register. This assumes interrupts are globally enabled by setting EA bit in IEN0 register. Figure 26. Timer Interrupt System TF0 TCON.5 ET0 IEN0.1 Timer 0 Interrupt Request TF1 TCON.7 ET1 IEN0.3 Timer 1 Interrupt Request |
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