AT89LS52 datasheet(17/39 Pages) ATMEL

17 / 39 page

AT89LS52

2601A–12/01

Programmable

Clock Out

A 50% duty cycle clock can be programmed to come out on P1.0, as shown in Figure 5. This

pin, besides being a regular I/O pin, has two alternate functions. It can be programmed to input

the external clock for Timer/Counter 2 or to output a 50% duty cycle clock ranging from 61 Hz

to 4 MHz (for a 16 MHz operating frequency).

To configure the Timer/Counter 2 as a clock generator, bit C/T2 (T2CON.1) must be cleared

and bit T2OE (T2MOD.1) must be set. Bit TR2 (T2CON.2) starts and stops the timer.

The clock-out frequency depends on the oscillator frequency and the reload value of Timer 2

capture registers (RCAP2H, RCAP2L), as shown in the following equation.

In the clock-out mode, Timer 2 roll-overs will not generate an interrupt. This behavior is similar

to when Timer 2 is used as a baud-rate generator. It is possible to use Timer 2 as a baud-rate

generator and a clock generator simultaneously. Note, however, that the baud-rate and clock-

out frequencies cannot be determined independently from one another since they both use

RCAP2H and RCAP2L.

Interrupts

The AT89LS52 has a total of six interrupt vectors: two external interrupts (INT0 and INT1),

three timer interrupts (Timers 0, 1, and 2), and the serial port interrupt. These interrupts are all

shown in Figure 6.

Each of these interrupt sources can be individually enabled or disabled by setting or clearing a

bit in Special Function Register IE. IE also contains a global disable bit, EA, which disables all

interrupts at once.

Note that Table 5 shows that bit position IE.6 is unimplemented. User software should not

write 1 to this bit position, since it may be used in future AT89 products.

Timer 2 interrupt is generated by the logical OR of bits TF2 and EXF2 in register T2CON. Nei-

ther of these flags is cleared by hardware when the service routine is vectored to. In fact, the

service routine may have to determine whether it was TF2 or EXF2 that generated the inter-

rupt, and that bit will have to be cleared in software.

The Timer 0 and Timer 1 flags, TF0 and TF1, are set at S5P2 of the cycle in which the timers

overflow. The values are then polled by the circuitry in the next cycle. However, the Timer 2

flag, TF2, is set at S2P2 and is polled in the same cycle in which the timer overflows.

Clock-Out Frequency

Oscillator Frequency

4 x [65536-(RCAP2H,RCAP2L)]

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