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STM32F745VG Fiches technique(PDF) 158 Page - STMicroelectronics |
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STM32F745VG Fiches technique(HTML) 158 Page - STMicroelectronics |
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158 / 227 page ![]() Electrical characteristics STM32F745xx STM32F746xx 158/227 DocID027590 Rev 4 Figure 47. SPI timing diagram - slave mode and CPHA = 1 Figure 48. SPI timing diagram - master mode I2S interface characteristics Unless otherwise specified, the parameters given in Table 77 for the I2S interface are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 17, with the following configuration: • Output speed is set to OSPEEDRy[1:0] = 10 • Capacitive load C = 30 pF • Measurement points are done at CMOS levels: 0.5VDD |
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