VDP313XY datasheet(23/76 Pages) MICRONAS

23 / 76 page

ADVANCE INFORMATION

VDP 313xY

Micronas

2.11.3.Average Beam Current Limiter

The average beam current limiter (BCL) uses the

sense input for the beam current measurement. The

BCL uses a different filter to average the beam current

during the active picture. The filter bandwidth is

approx. 2 kHz. The beam current limiter has an auto-

matic offset adjustment that is active two lines before

the first cutoff measurement line.

The beam current limiter function is located in the

front-end. The data exchange between the front-end

and the back-end is done via a single-wire serial inter-

face.

The beam current limiter allows the setting of a thresh-

old current. If the beam current is above the threshold,

the excess current is lowpass filtered and used to

attenuate the RGB outputs by adjusting the whitedrive

multipliers for the internal (digital) RGB signals, and

the analog contrast multipliers for the analog RGB

inputs, respectively. The lower limit of the attenuator is

programmable, thus a minimum contrast can always

be set. During the tube measurement, the ABL attenu-

ation is switched off. After the whitedrive measurement

line it takes 3 lines to switch back to BCL limited drives

and brightness.

Typical characteristics of the ABL for different loop

gains are shown in Fig. 2–20; for this example the tube

has been assumed to have square law characteristics.

Fig. 2–20: Beam current limiter characteristics:

beam current output vs. drive

BCL threshold: 1

2.11.4.Analog RGB Insertion

The VDP 313xY allows insertion of 2 external analog

RGB signals. Each RGB signal is key-clamped and

inserted into the main RGB by the fast blank switch.

The selected external RGB input is virtually handled as

a priority bus signal. Thus, it can be overlaid or under-

laid to the digital picture. The external RGB signals can

be adjusted independently as regards DC-level (bright-

ness) and magnitude (contrast).

Which analog RGB input is selected depends on the

fast blank input signals and the programming of a num-

ber of I2C-bus register settings (see Table 2–2 and Fig.

2–21). Both fast blank inputs must be either active-low

or active-high.

All signals for analog RGB insertion (RIN1/2, GIN1/2,

BIN1/2, FBLIN1/2, HCS) must be synchronized to the

horizontal flyback, otherwise a horizontal jitter will be

visible. The VDP 313xY has no means for timing cor-

rection of the analog RGB input signals.

Table 2–2: RGB Input Selection

FBFOH1=0, FBFOH2=0, FBFOL1=0, FBFOL2=0

FBLIN1

FBLIN2

FBPOL

FBPRIO

RGB output

Video

RGB input 2

RGB input 1

RGB input 2

RGB input 1

RGB input 2

RGB input 1

RGB input 2

Video

VDP313XY Fiches technique(PDF) 23 Page - Micronas

VDP313XY Fiches technique(HTML) 23 Page - Micronas

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76

Fiches technique Télécharger

Lien URL