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QL8050 Fiches technique(PDF) 30 Page - List of Unclassifed Manufacturers

No de pièce QL8050
Description  LOW POWER FPGA COMBINING PERFORMANCE DENSITY AND EMBEDED RAM
PDF  49 Pages
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Fabricant  ETC [List of Unclassifed Manufacturers]
Site Internet  
Logo ETC - List of Unclassifed Manufacturers

QL8050 Fiches technique(HTML) 30 Page - List of Unclassifed Manufacturers

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Preliminary

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tIRST
Input register reset delay: time between when the flip-flop is “reset”(low) and when
the output is consequently “reset” (low)
-
0.99 ns
tIESU
Input register clock enable setup time: time “enable” must be stable before the
active clock edge
0.37 ns
-
tIEH
Input register clock enable hold time: time “enable” must be stable after the active
clock edge
0 ns
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