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PC87591L Fiches technique(PDF) 82 Page - National Semiconductor (TI) |
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PC87591L Fiches technique(HTML) 82 Page - National Semiconductor (TI) |
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82 / 437 page ![]() 4.0 Embedded Controller Modules (Continued) www.national.com 82 Revision 1.07 Core Bus Monitoring The core bus monitoring cycle is a non-data transfer bus cycle. It takes a single clock cycle - T1. On this cycle: ● The address pins display the address of the internal device accessed on the core bus. ● CBRD indicates the direction of the access (read or write). ● BE0-1 indicate which data bus bytes are accessed (lower or upper). ● BST0-2 display the core bus status. The core bus monitoring cycle, as shown in Figure 26, is generated only when bit 1 (OBR) in BCFG register is 1. CLK A0-12, T1 SEL0-1 WR0-1 D0-15 RD BST0-2 SELIO A16-19 CBRD BE0-1 Figure 26. Core Bus Monitoring Bus Cycle Bus State |
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