PC87591L datasheet(29/437 Pages) NSC

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1.0 Introduction (Continued)

Revision 1.07

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The Mobile System Wake-Up module includes various system wake-up and power management services that may be

handled either by the host or the core. ¨(wake-upsources may be the RTC or external events such as ring detection on the

RING input or modem RI inputs. The module provides hooks for ACPI-compliant drivers, which enable the drivers to handle

wake-up events, change the system power state (including turning it off) and interface to the core firmware. Mask bits can

be enabled to determine whether the core or the host handles each one of the events. In addition, this module provides sta-

tus information about the host domain (e.g., reset input state and VDD supply status).

The Core Access to Host-Controlled Peripherals module enables core access to SuperI/O modules. It can interleave us-

age of a module with the host or take control of it and prevent any host access to that module.

1.3.6

Host-Controlled SuperI/O Modules and Host Interface

The Host Interface is based on Intel’s Low Pin Count (LPC) interface, as defined in LPC Interface Specification, Revision

1.0. This interface enables the host to perform read and write cycles using I/O space accesses and memory space accesses

and FWH transactions. Interrupts are sent to the host, using the serial IRQ protocol.

The PC87591x supports the advanced power management features of the LPC bus. The SMI signal may be sent to interrupt

the host and put it in System Management Mode (SMM). The PWUREQ signal may be connected to one of the wake-up

inputs of the host chipset and used to trigger an SCI event for various EC communication purposes. The PC87591x can

operate with a slowed down or stopped LPC clock and can re-start the LPC clock as part of the system power management

capabilities, using the CLKRUN signal. The LPCPD input enables turning off LPC bus supply while the PC87591x and some

Host Controlled functions are operating.

Host Conﬁguration. The PC87591x includes seven logical devices, each with associated configuration registers, in addi-

tion to a set of global configuration registers.

The central configuration register set supports ACPI-compliant PnP configuration. The configuration registers are structured

as a subset of the Plug and Play Standard registers defined in Appendix A of the Plug and Play ISA Specification, Revision

1.0a by Intel and Microsoft. All system resources assigned to the functional blocks (I/O address space and IRQ lines) are

configured in and managed by the central configuration register set. In addition, some function-specific parameters are con-

figurable through the configuration registers and distributed to the functional blocks through special control signals.

The RTC (Real Time Clock) has a low-power timekeeping mechanism that provides a time-of-day, year-2000-compatible

calendar with a century counter and alarm features. It can work from either VCC or a backup battery, using an internal switch.

Other features include three maskable interrupt sources and 242 bytes of general-purpose RAM. An external battery source

maintains valid RAM and time during VCC failure. The RTC is software compatible with the DS1287 and MC146818.

1.4

OPERATING ENVIRONMENTS

On power-up reset, the ENV1-0 and TRIS input signals select one of the following operating environments:

●

Internal ROM Enabled (IRE)

●

On Board Development (OBD)

●

Development (DEV)

●

Programing (PROG)

See Section 2.3 on page 53 for more information about these pins and controlling the loads connected to them.

Code written for IRE environment is executable in all environments, since it is binary compatible. The execution time of code

in on-chip Base Memory (in IRE environment) is identical to that in OBD and DEV environments; i.e., the operation is cycle-

by-cycle compatible.

PC87591x devices are tested to ensure that they operate in either IRE or OBD environment. Only selected parts are tested

for operation in DEV environment.

1.4.1

IRE Environment

IRE environment is used while the PC87591x operates in the production system and executes the application. The on-chip

flash (ROM in PC87591L) is the main source of code for the device. In this environment, after reset, the PC87591x starts

running the code written in the internal flash first address, which is part of the flash’s core boot block. In PC87591E and

PC87591S the core boot-code size may vary from 4 Kbytes to128 Kbytes, as defined in the protection word. To prevent ex-

ecution from non-programed flash (typically due to interrupted update), the code in the boot sector should verify the validity

of the information in other parts of the flash. Once this is successfully done, the core may start executing from these parts

as well. The External Memory, if available, can also be used to store code and/or data.

The PC87591L is shipped with 4 Kbytes of on-chip boot code. The user is expected to use an external memory for most of

the code and constant data.

To maximize on-chip flash (ROM) performance, configure the BIU as described in Section 4.1.11 on page 86 and

Section 4.16.2 on page 219.

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