MCLK _IN

C

MCLK

CDC3RL02

www.ti.com

SCHS371C – NOVEMBER 2009 – REVISED JANUARY 2016

9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

9.1 Application Information

9.1.1 Input Clock Squarer

Figure 11 shows the input stage of the CDC3RL02. The input signal at MCLK_IN can be a square wave or sine

CDC3RL02 without an external capacitor.

Figure 11. Input Stage with Internal AC Coupling Capacitor

Any external component added in the series path of the clock signal will potentially add phase noise and jitter.

The error source associated with the internal decoupling capacitor is included in the specification of the

CDC3RL02. The recommended clock frequency band of the CDC3RL02 is 10 MHz to 52 MHz for specified

functionality. All performance metrics are specified at 26 MHz. The lowest acceptable sinusoidal signal amplitude

and jitter performance.

9.1.2 Output Stage

Each output drives 1.8-V LVCMOS levels. Adaptive output buffers limit the rise/fall time of the output to within 1

ns to 5 ns with load capacitance between 10 pF and 50 pF. Fast slew rates introduce EMI into the system. Each

output buffer limits EMI by keeping the rise/fall time above 1 ns. Slow rise/fall times can induce additive phase

noise and duty cycle errors in the load device. The output buffer limits these errors by keeping the rise/fall time

below 5 ns. In addition, the output stage dynamically alters impedance based on the instantaneous voltage level

of the output. This dynamic change limits reflections keeping the output signal monotonic during transitions. Each

output is active low when not requested to avoid false clocking of the load device.

9.1.3 LDO

A low noise 1.8-V LDO is integrated to provide the I/O supply for the output buffers. The LDO output is externally

available to power a clock source such as a TCXO. A clean supply is provided to the clock buffers and the clock

source for optimum phase noise performance. The input range of the LDO allows the device to be powered

directly from a single cell Li battery. The LDO is enabled by either of the CLK_REQ_N signals. When disabled,

the device enters a low power shutdown mode consuming less than 1

μA from the battery. The LDO requires an

output decoupling capacitor in the range of 1

μF to 10 μF for compensation and high frequency PSR. This

capacitor must stay within the specified range over the entire operating temperature range. An input bypass

capacitor of 1

μF or larger is recommended.

Copyright © 2009–2016, Texas Instruments Incorporated

Submit Documentation Feedback

11

Product Folder Links: CDC3RL02