| Moteur de recherche de fiches techniques de composants électroniques |
|
CDC3RL02YFPR Fiches technique(PDF) 9 Page - Texas Instruments |
|
|
|
|||||||||||||||||||||||||||||
CDC3RL02YFPR Fiches technique(HTML) 9 Page - Texas Instruments |
|
9 / 20 page ![]() V BATT GND MCLK_IN LDO Switch/ Decoder EN V CC V LDO CLK_OUT1 CLK_REQ1 CLK_OUT2 CLK_REQ2 EN V CC CDC3RL02 www.ti.com SCHS371C – NOVEMBER 2009 – REVISED JANUARY 2016 8 Detailed Description 8.1 Overview The CDC3RL02 is a two-channel clock fan-out buffer and is ideal for use in portable end-equipment, such as mobile phones, that require clock buffering with minimal additive phase noise and fan-out capabilities. It buffers a single master clock, such as a temperature compensated crystal oscillator (TCXO) to multiple peripherals. The device has two clock request inputs (CLK_REQ1 and CLK_REQ2), each of which enable a single clock output. The CDC3RL02 accepts square or sine waves at the master clock input (MCLK_IN), eliminating the need for an AC coupling capacitor. The smallest acceptable sine wave is a 0.3-V signal (peak-to-peak). CDC3RL02 has been designed to offer minimal channel-to-channel skew, additive output jitter, and additive phase noise. The adaptive clock output buffers offer controlled slew-rate over a wide capacitive loading range which minimizes EMI emissions, maintains signal integrity, and minimizes ringing caused by signal reflections on the clock distribution lines. The CDC3RL02 has an integrated Low-Drop-Out (LDO) voltage regulator which accepts input voltages from 2.3 V to 5.5 V and outputs 1.8 V, 50 mA. This 1.8-V supply is externally available to provide regulated power to peripheral devices such as a TCXO. 8.2 Functional Block Diagram 8.3 Feature Description 8.3.1 Low Additive Noise The CDC3RL02 features –149 dBc/Hz at 10 kHz offset phase noise and 0.37 ps (RMS) of output jitter, to make sure that the buffered signals are clean. 8.3.2 Regulated 1.8-V Externally Available I/O Supply The CDC3RL02 allows users to connect to the output of the internal LDO, for providing power to other ICs. For more information, refer to LDO. 8.3.3 Ultra-Small 8-bump YFP 0.4-mm Pitch WCSP Package Using the ultra-small YFP package, the CDC3RL02 is very small and allows it to be placed on a board with minimum work. Copyright © 2009–2016, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Links: CDC3RL02 |
|
|
Lien URL |
| ALLDATASHEET vous a-t-il été utile ? [ DONATE ] |
À propos de Alldatasheet | Publicité | Contactez-nous | Politique de confidentialité | Lien vers la fiche technique | Echange de liens | Fabricants All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |