DP83256 datasheet(90/144 Pages) NSC

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60 Signal Descriptions (Continued)

PHY PORT INTERFACE

The PHY Port Interface consists of IO signals used to connect the PLAYERa device to the Media Access Control (MAC)

sublayer or other PLAYERa device The DP83256 Device has two PHY Port Interfaces The A

Indicate path from one PHY

Port Interface and the B

Request path from the second PHY Port Interface Each path consists of an odd parity bit a control

bit and two 4-bit symbols

Refer to section 33 the Configuration Switch for more information

Symbol

Description

AIP

PHY Port A Indicate Parity

A TTL output signal representing odd parity for the 10-bit wide Port A

Indicate signals (AIP AIC and AIDk70l)

AIC

PHY Port A Indicate Control

TTL output signal indicating that the two 4-bit symbols (AIDk74l and

AIDk30l) are either control symbols (AICe1) or data symbols (AICe0)

AID7

PHY Port A Indicate Data

TTL output signals representing the first 4-bit datacontrol symbol

AID6

AID7 is the most significant bit and AID4 is the least significant bit of the first symbol

AID5

AID4

AID3

PHY Port A Indicate Data

TTL output signals representing the second 4-bit datacontrol symbol

AID2

AID3 is the most significant bit and AID0 is the least significant bit of the second symbol

AID1

AID0

BRP

PHY Port B Request Parity

A TTL input signal representing odd parity for the 10-bit wide Port A

Request signals (BRP BRC and BRDk70l)

BRC

PHY Port B Request Control

A TTL input signal indicating that the two 4-bit symbols

(BRDk74l and BRDk30l) are either control symbols (BRCe1) or data symbols (BRCe0)

BRD7

PHY Port B Request Data

TTL input signals representing the first 4-bit datacontrol symbol

BRD6

BRD7 is the most significant bit and BRD4 is the least significant bit of the first symbol

BRD5

BRD4

BRD3

PHY Port B Request Data

TTL input signals representing the second 4-bit datacontrol symbol

BRD2

BRD3 is the most significant bit and BRD0 is the least significant bit of the second symbol

BRD1

BRD0

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