CLC533 datasheet(8/9 Pages) NSC

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Mixed Mode Circuit Design

In any mixed mode circuit care must be taken to keep the

high slew-rate digital signals from interfering with the high

precision analog signals. A successful design will take

this into consideration from many angles and will account

for it in digital timing, logic family selected, PCB layout,

analog signal bandwidth and a myriad of other aspects.

Below are a few tips that should be kept in mind when

designing a circuit that involves both analog and digital

circuitry.

Timing

If the analog signals going through the CLC533 are to be

sampled, try to minimize the amount of digital logic

switching concurrent with the sampling instant.

Power Supply Net

In an analog system the ideal situation would have each

circuit element completely isolated from all others except

for the intended connections. One of the most common

ways for unwanted connections to be made is through the

power supplies and ground. These are often shared by

all of the circuits in the system. Refer to the section on

power supplies and grounding for tips on how to avoid these

pitfalls.

Logic Family Selection

When designing digital logic, there are often several logic

families that will provide a solution to the problem at

hand.

Although they may perform equally in a

digital sense, they may have varying degrees of

influence on the analog circuits in the same system.

Coupling of digital signals with analog signals through

stray capacitances is rarely a problem for the digital logic

but can be a detrimental to an otherwise good analog

design.

To minimize coupling, lay out the board to

minimize

the

stray

capacitances

much

possible: if an analog and a digital signal must cross,

make them cross at right angles and avoid long

parallel runs. If a 74LS00 will work in a socket, using a

74F00 will probably have no effect on the digital

circuitry, but the faster edges will find it easier to

corrupt analog signals.

When faced with a choice

between several logic families, select the slowest one

possible to get the job done. Don’t forget that the slew

rates of digital logic depend not only on the rise and fall

times, but on the output swing as well. ECL gates with a

1ns rise time have much slower slew rates than TTL

gates with the same rise times. Do not attempt to slow

logic edge rates through the addition of capacitance on

the logic lines.

The negative effects that digital logic has on power supplies

is not constant through different logic families. CMOS

logic draws current only during transitions. The surge

currents that it draws at these times can be quite significant

and can be very disruptive to the power and ground net-

works. ECL tends to draw constant amounts of current

and has a much smaller effect on the power net.

Gain Selection for an ADC

In many applications, such as RADAR, the dynamic

range

requirements

may

exceed

the

accuracy

requirements. Since wide dynamic range ADCs are also

typically highly accurate ADCs this often leads the

designer into an ADC which is a technical overkill and a

budget buster. By using the CLC533 as a selectable gain

stage, a less expensive A/D can be used. For example, if

an application calls for 85dB of dynamic range and 0.05%

accuracy, rather than using a 16 bit converter, use a 12

bit converter with the circuit shown below. In this circuit

the CLC533 is used to select between the input signal

and version of the input signal attenuated by 6, 12 and

18dB.

This circuit affords better than 14 bit dynamic

range, 12 bit accuracy and a 12 bit price.

By using

resistors of all the same value, a single resistor network

can be used which can assure good matching of the

resistors, even over temperature.

Figure 6

Evaluation Board

Evaluation boards are available for both the DIP

versions (Part number CLC730035) and SOIC version

(part number CLC730039) of the CLC533. These boards

can be used for fast, trouble free evaluation and charac-

terization of the CLC533. Additionally this board serves

an example of a successful PCB layout that can be

copied into applications circuits. A separate data sheet

for the evaluation board can be obtained.

Vin

CLC533

Vout

Gain Select

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