RT9451 datasheet(3/37 Pages) RICHTEK

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RT9451

DS9451-00

September 2013

www.richtek.com

is a registered trademark of Richtek Technology Corporation.

Functional Pin Description

Pin No.

Pin Name

Pin Function

1 to 4

VIN

Power Input. Bypass to PGND with a 10

μF ceramic capacitor. It also provides

power to the load in boost mode.

INT

Interrupt Pin (Open-Drain). This pin is pulled low when a fault occurs.

VIO

I/O Reference Voltage. A VIO level above 0.6V disables automatic D+/D

−

detection.

USB Port D+ Input Connection.

USB Port D

− Input Connection.

SCL

C Interface Clock Input. Open-drain output, connect a 10k

Ω pull-up resistor.

SDA

C Interface Data Input. Open-drain output, connect a 10k

Ω pull-up resistor.

STAT

Charge Status Indicator. Pull low when charge is in progress. Open-drain for

other conditions. This pin can also be controlled through I

C register. The STAT

can be used to drive a LED or communicate with a host processor.

OTG

Boost Mode Enable Control. Boost mode is turned on whenever this pin is active.

Polarity is user defined through I

C register. The pin is disabled by default and

can be enabled through I

C register bit.

BATS

Auxiliary Power Supply. Connect to the battery pack to provide power in high

impedance mode. Bypass to GND with a 1

μF ceramic capacitor.

ISENL

Charge Current Sense Input. Battery current is sensed via the voltage drop

across an external sense resistor. A 0.1

μF ceramic capacitor to PGND is

required.

ISENR

Battery Voltage and Current Sense Input. Bypass to PGND with a ceramic

capacitor (minimum 0.1

μF) if there are long inductive leads to battery.

LDO

LDO Output. LDO is regulated to 4.9V and drives 60mA of current. Bypass LDO

to GND with a minimum 1

μF ceramic capacitor. LDO is enabled when VIN is

above the VIN UVLO threshold.

MID_LDO

LDO Input Voltage. Please connect to MID.

BOOT

Bootstrap Supply for High-Side Gate Driver. Connect a 100nF ceramic capacitor

(voltage rating above 10V) from BOOT pin to LX pin.

VDDP

Internal Bias Regulator Voltage for Driver. Connect a 1

μF ceramic capacitor from

this output to PGND. External loads on VDDP is not allowed.

20, 33

(Exposed Pad)

GND

Pure Ground. The exposed pad must be soldered to a large PCB and connected

to GND for maximum thermal dissipation.

21 to 25

PGND

Power Ground.

26 to 30

Switch Node.

31, 32

MID

Connection Point Between Reverse Blocking MOSFET and High-Side MOSFET.

Bypass to PGND with a minimum of 10

μF capacitor. No other circuits are

recommended to connect at MID pin.

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