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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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LED1642GWPTR Fiches technique(PDF) 26 Page - STMicroelectronics |
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LED1642GWPTR Fiches technique(HTML) 26 Page - STMicroelectronics |
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26 / 42 page  Configuration register LED1642GW 26/42 DocID024395 Rev 6 Figure 21. SDO delay 8.7 Gradual output delay (CFG-14) The gradual output delay consists of turning on gradually the current generators avoiding to turn on all channels at the same time. When PWM counter enables the device channels, the outputs can be turned on simultaneously or with a progressive delay. Thanks to configuration register CFG -14 bit, the user can decide to put a delay among outputs (10 ns from each channel to the next one, around 150 ns between first and last channel). The typical output timing is shown in Figure 22. This feature prevents the inrush current and reduces the bypass capacitor value. AM13702V1 (a) (b) (a) Data shifted out of the SDO with the device propagation delay (b) Data shifted out of the SDO by the falling edge of the CLK |
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