PIC16F628-20SLASHP datasheet(83/160 Pages) MICROCHIP

83 / 160 page

Preliminary

DS40300B-page 83

PIC16F62X

12.3

USART Function

The USART function is similar to that on the

PIC16C74B, which includes the BRGH = 1 fix.

12.3.1

USART 9-BIT RECEIVER WITH ADDRESS

DETECT

When the RX9 bit is set in the RCSTA register, 9-bits

are received and the ninth bit is placed in the RX9D bit

of the RCSTA register. The USART module has a spe-

cial provision for multi-processor communication. Mul-

tiprocessor communication is enabled by setting the

ADEN bit (RCSTA<3>) along with the RX9 bit. The port

is now programmed such that when the last bit is

received, the contents of the receive shift register

(RSR) are transferred to the receive buffer, the ninth bit

of the RSR (RSR<8>) is transferred to RX9D, and the

receive interrupt is set if and only if RSR<8> = 1. This

feature can be used in a multi-processor system as fol-

lows:

A master processor intends to transmit a block of data

to one of many slaves. It must first send out an address

byte that identifies the target slave. An address byte is

identified by setting the ninth bit (RSR<8>) to a ’1’

(instead of a ’0’ for a data byte). If the ADEN and RX9

bits are set in the slave’s RCSTA register, enabling mul-

tiprocessor communication, all data bytes will be

ignored. However, if the ninth received bit is equal to a

‘1’, indicating that the received byte is an address, the

slave will be interrupted and the contents of the RSR

allows the slave to be interrupted only by addresses, so

that the slave can examine the received byte to see if it

is being addressed.

The addressed slave will then

clear its ADEN bit and prepare to receive data bytes

from the master.

When ADEN is enabled (='1'), all data bytes are

ignored. Following the STOP bit, the data will not be

loaded into the receive buffer, and no interrupt will

occur. If another byte is shifted into the RSR register,

the previous data byte will be lost.

The ADEN bit will only take effect when the receiver is

configured in 9-bit mode (RX9 = '1'). When ADEN is

disabled (='0'), all data bytes are received and the 9th

bit can be used as the parity bit.

The receive block diagram is shown in Figure 12-8.

Reception is enabled by setting bit CREN (RCSTA<4>).

12.3.1.1

SETTING UP 9-BIT MODE WITH

ADDRESS DETECT

Steps to follow when setting up an Asynchronous or

Synchronous Reception with Address Detect Enabled:

Initialize the SPBRG register for the appropriate

baud rate. If a high speed baud rate is desired,

set bit BRGH.

Enable asynchronous or synchronous commu-

nication by setting or clearing bit SYNC and set-

ting bit SPEN.

If interrupts are desired, then set enable bit

RCIE.

Set bit RX9 to enable 9-bit reception.

Set ADEN to enable address detect.

Enable the reception by setting enable bit CREN

or SREN.

Flag bit RCIF will be set when reception is com-

plete, and an interrupt will be generated if

enable bit RCIE was set.

Read the 8-bit received data by reading the

RCREG register to determine if the device is

being addressed.

If any error occurred, clear the error by clearing

enable bit CREN if it was already set.

10. If the device has been addressed (RSR<8> = 1

with address match enabled), clear the ADEN

and RCIF bits to allow data bytes and address

bytes to be read into the receive buffer and inter-

rupt the CPU.

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