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9FGL02 Fiches technique(PDF) 14 Page - Integrated Device Technology

No de pièce 9FGL02
Description  control input polarity
PDF  19 Pages
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Fabricant  IDT [Integrated Device Technology]
Site Internet  http://www.idt.com
Logo IDT - Integrated Device Technology

9FGL02 Fiches technique(HTML) 14 Page - Integrated Device Technology

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2-OUTPUT 3.3V PCIE GEN 1-2-3 CLOCK GENERATOR
14
REVISION A 07/17/15
9FGL02 DATASHEET
SMBus Table: Pull-up Pull-down Control
Byte 16
Name
Control Function
Type
0
1
Default
Bit 7
0
Bit 6
0
Bit 5
1
Bit 4
0
Bit 3
0
Bit 2
1
Bit 1
CKPWRGD_PD_pu/pd[1]
RW
00=None
10=Pup
1
Bit 0
CKPWRGD_PD_pu/pd[0]
RW
01=Pdwn
11 = Pup+Pdwn
0
Byte 17 is Reserved
SMBus Table: Polarity Control
Byte 18
Name
Control Function
Type
0
1
Default
Bit 7
0
Bit 6
0
Bit 5
OE1_polarity
Sets OE1 polarity
RW
Enabled when Low Enabled when High
0
Bit 4
0
Bit 3
OE0_polarity
Sets OE0 polarity
RW
Enabled when Low Enabled when High
0
Bit 2
0
Bit 1
0
Bit 0
0
SMBus Table: Polarity Control
Byte 19
Name
Control Function
Type
0
1
Default
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
CKPWRGD_PD
Determines
CKPWRGD_PD polarity
RW
Power Down when
Low
Power Down when
High
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
CKPWRGD_PD Pull-up(PuP)/
Pull-down(Pdwn) control



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