 |
Moteur de recherche de fiches techniques de composants électroniques |
|
|
Moteur de recherche de fiches techniques de composants électroniques |
|
9FGL02 Fiches technique(PDF) 1 Page - Integrated Device Technology |
|
|
|||||||||||||||||||||||||||||
9FGL02 Fiches technique(HTML) 1 Page - Integrated Device Technology |
|
|
1 / 19 page  DATASHEET 9FGL02 REVISION A 07/17/15 1 ©2015 Integrated Device Technology, Inc. 2-output 3.3V PCIe Gen 1-2-3 Clock Generator 9FGL02 Description The 9FGL0241/51/P1 are members of IDT's 3.3V Low-Power (LP) PCIe family. The devices have 2 output enables for clock management and support 2 different spread spectrum levels in addition to spread off. The 9FGL0241/51/P1 supports both Common Clock (CC) with or without spread spectrum and Separate Reference no-Spread (SRnS) PCIe clocking architectures. The 9FGL02P1 can be programmed with a user-defined power up default SMBus configuration. Recommended Application 3.3V PCIe Gen1-2-3 Clock Generator Output Features • 2 – 100 MHz Low-Power HCSL (LP-HCSL) DIF pairs • 9FGL0241 default ZOUT = 100 • 9FGL0251 default ZOUT = 85 • 9FGL02P1 factory programmable defaults • 1 - 3.3V LVCMOS REF output w/Wake-On-LAN (WOL) support Key Specifications • DIF cycle-to-cycle jitter <50ps • DIF output-to-output skew <50ps • DIF phase jitter is PCIe Gen1-2-3 compliant with SSC on or off • DIF 12k-20M phase jitter is <3ps rms when SSC is off • REF phase jitter is <300fs rms (SSC off) and < 1ps RMS (SSC on) • ±100ppm frequency accuracy on all clocks Features/Benefits • Direct connection to 100 (xx41) or 85 (xx51) transmission lines; saves 8 resistors compared to standard PCIe devices • 112mW typical power consumption; eliminates thermal concerns • SMBus-selectable features allows optimization to customer requirements: • control input polarity • control input pull up/downs • slew rate for each output • 33, 85 or 100Ω output impedance for each output • spread spectrum amount • 41 and 51 devices contain default configuration; SMBus interface not required for device operation • P1 device allows factory programming of customer-defined SMBus power up default; allows exact optimization to customer requirements • OE# pins; support DIF power management • 8MHz – 40MHz input frequency (25MHz default); flexibility • Pin/SMBus selectable 0%, -0.25% or -0.5% spread on DIF outputs %; minimize EMI and phase jitter for each application • DIF outputs blocked until PLL is locked; clean system start-up • Two selectable SMBus addresses; multiple devices can easily share an SMBus segment • Space saving 24-pin 4x4mm VFQFPN; minimal board space Block Diagram Note: Resistors default to internal on 41/51 devices. P1 devices have programmable default impedances on an output-by-output basis. XIN/CLKIN_25 X2 CONTROL LOGIC vSS_EN_tri ^CKPWRGD_PD# SDATA_3.3 SS Capable PLL OSC REF vOE(1:0)# SCLK_3.3 vSADR DIF1 DIF0 XIN/CLKIN_25 X2 CONTROL LOGIC vSS_EN_tri ^CKPWRGD_PD# SDATA_3.3 SS Capable PLL OSC REF vOE(1:0)# SCLK_3.3 vSADR DIF1 DIF0 |
Numéro de pièce similaire - 9FGL02 |
|
Description similaire - 9FGL02 |
|
|
|
Lien URL |
| ALLDATASHEET vous a-t-il été utile ? [ DONATE ] |
À propos de Alldatasheet | Publicité | Contactez-nous | Politique de confidentialité | Lien vers la fiche technique | Echange de liens | Fabricants All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
French ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
