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AN1042 Fiches technique(PDF) 4 Page - STMicroelectronics

No de pièce AN1042
Description  ST7 ROUTINE FOR I2C SLAVE MODE MANAGEMENT
PDF  8 Pages
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Fabricant  STMICROELECTRONICS [STMicroelectronics]
Site Internet  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

AN1042 Fiches technique(HTML) 4 Page - STMicroelectronics

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ST7 ROUTINE FOR I2C SLAVE MODE MANAGEMENT
When the address received matches, the interface generates in sequence:
- Acknowledge pulse if the ACK bit is set.
- EVF and ADSL are set with an interrupt if ITE bit is set.
Then the interface waits for a read of SR1 register, holding the SCL line low. Then it deter-
mines from the TRA bit of the SR1 register if the slave has to be receiver or transmitter.
- TRA = 0: Data byte received (if BTF=1)
- TRA=1: Data byte transmitted
2.2.3 Receiving Data on the I2C Bus
The slave then receives bytes from the SDA line into the DR register via the internal shift in-
terface. After each byte, the interface generates in sequence:
- Acknowledge pulse if the ACK bit is set.
- EVF and BTF bits are set with an interrupt if ITE bit is set.
Then the interface waits for a read of the SR1 register followed by a read of the DR register
(see Transfer Sequencing).
After each reception, the data bytes received are placed in a table. If an error occurs, the in-
terface is re-initialized (I2CCR cleared and put to its initial value after having removed pending
interrupts) and the slave waits for next start condition.
2.2.4 Sending Data on the I2C Bus
When the slave receives start condition and matching slave address (with LSB set) from the
master, it becomes transmitter and then sends the master back data it stored into a table. It
sends data from DR register to the SDA line via the internal shift register.
The slave waits for a read of the SR1 register followed by a write of next data into the DR reg-
ister (see Transfer Sequencing).
When the acknowledge pulse is received:
- the EVF and BTF bits are set by hardware with an interrupt if ITE bit is set.
After the last data byte is transferred, a Stop condition is generated by the master. The inter-
face detects this condition and sets:
- EVF and STOPF bits with an interrupt if ITE bit is set.
Then the interface waits for a read of the SR2 register.
In this application, the TRA bit of the SR1 register is used as a flag to determine the mode (re-
ceiver or transmitter) of the microcontroller.



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