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AN4218 Fiches technique(PDF) 13 Page - STMicroelectronics |
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AN4218 Fiches technique(HTML) 13 Page - STMicroelectronics |
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13 / 26 page ![]() DocID024014 Rev 2 13/26 AN4218 Good practices of system power supply Figure 11. Measurement over the entire pulse 1. Line 1 (RST): NRESET output Line 2 (V1): microcontroller power supply VDD Line 3 (VBAT): system power supply (VBAT) Line 4 (OUT_HS): high-side driver output Line D4 (CSN): SPI-logic signal chip-select-not Line D5 (OUT_LS): low-side driver output Line D7 (FSO): fail-safe state (internal signal) Figure 12. Zoom into the low voltage drop region 1. Line 1 (RST): NRESET output Line 2 (V1): microcontroller power supply VDD Line 3 (VBAT): system power supply (VBAT) Line 4 (OUT_HS): high-side driver output Line D4 (CSN): SPI-logic signal chip-select-not Line D5 (OUT_LS): low-side driver output Line D7 (FSO): fail-safe state (internal signal) |
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