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80960SA Fiches technique(PDF) 37 Page - Intel Corporation |
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80960SA Fiches technique(HTML) 37 Page - Intel Corporation |
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37 / 39 page ![]() RESET CLK2 CLK VCC AS, DT/R, DEN, LOCK (O) HLDA BLAST/FAIL ALE, A31:16, A15:4, A3:1, D15:0, BE1:0, W/R INT0, INT1, INT3, LOCK (I) VCC and CLK2 stable to RESET high, minimum 41 CLK2 periods Initialization parameters set up to first A edge, minimum 4 CLK2 periods First Bus Activity Internal self-test, approximately 94,000 CLK2 periods (if selected) A B C D Ta A B C D A B C D A B C D A B C D A B C D 48,000 VALID |
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