2

ICS9120-46

Pin Configuration

Pin Descriptions for ICS9120-46

Functionality

X1 (MHz)

PD#

CLK1

(MHz)

CLK2

(MHz)

REF

(MHa)

-

0

Low

Low

Low

14.7456

1

49.92

40.32

14.7456

8-Pin SOIC

PIN

N U M BER

PIN

NA M E

T YPE

D ESC RIPTIO N

1

X 1

Input

Crystal or external clock source. H as feedback bias for crystal.

N om inally 14.7456<N> M H z input applied. (N o internal load cap;

m ust connect external load cap to ground for crystal oscillator.)

2

V DD

Pow er

+Pow er supply input.

3

G ND

Pow er

G round return for Pin 2.

4

C LK1

O utput

49.92 M H z target output clock

(w ith nom inal 14.7456 M H z input).

5

PD #

O utput

Power-down input. A ll outputs shut off and driven to low output state

w hen this pin is at logic low level. H as pull-up.

6

C LK2

O utput

40.32 M H z target output clock.

7

R EF

O utput

14.7456 M Hz reference clock buffered output

(w ith nom inal 14.7456 M H z input).

8

X2

Output

Crystal output drive (leave this pin unconnected when using an

external clock). (N o internal load cap; m ust connect external load cap

to ground for crystal oscillator).

Functionality

The ICS9120-46 incorporates a crystal oscillator circuit designed

to provide 50% duty cycle over a range of operating conditions,

including the addition of external crystal load capacitors to pins

X1 and X2.

For the crystal oscillator, the crystal load capacitance must be

connected externally by adding a capacitor from each of the X1

and X2 pins to ground. A parallel resonant 14.7456 MHz crystal is

recommended.

Duty cycle is also maintained when using an external clock source

(connected to X1, X2 left unconnected) as long as the external

clock has good duty cycle.