MDS 1523 Y

17

Revision 110905

Integrated Circuit Systems

525 Race Street, San Jose, CA 95126

tel (408) 297-1201

www.icst.com

ICS1523

12.3 HSYNC to REF Timing

Figure 12-4 HSYNC to REF Timing Diagram

Table 12-4 HSYNC to REF Timing Diagram

12.4 CLK/2 Timing for Odd and Even Feedback Divider

Figure 12-5 CLK/2: Even versus Odd

For simplicity, the waveforms drawn show only the identical PECL CLK/2+ and the SSTL_3 CLK/2 signals. CLK/2-

is the compliment of the CLK/2+ signal.

Note that regardless of the CLK\2 phase at the assertion of FUNC, the clocks always have the same phase at the

fall of FUNC, regardless of 0x2

Symbol Parameter

Minimum

Typical

Maximum

Units

HSYNC Low to REF Delay

6

7.5

8.5

ns

HSYNC High to REF Delay

3.5

4.3

6

ns

REF

HSYNC

Reg0:2 = 1

REF

HSYNC

t1

Reg0:2 = 0

t1

t0

FUNC

CLK/2

Even - Reg2:0=0

CLK/2

Odd - Reg2:0=1