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HM17CM256 Fiches technique(PDF) 97 Page - Hynix Semiconductor |
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HM17CM256 Fiches technique(HTML) 97 Page - Hynix Semiconductor |
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97 / 111 page ![]() HM17CM256 - 97 - s AC CHARACTERISTICS • SYSTEM BUS READ / WRITE TIMING (80 series CPU interface) (write timing) (VDD=2.7 ∼3.3V, Ta=-30∼+85°C) ITEM SYMBOL CONDITION MIN. MAX. UNIT PORT Address hold timing Address setup timing tAH8 tAS8 TBD TBD ns ns CS RS System cycle timing Write ”L” pulse width Write ”H” pulse width tCYC8 tWRLW8 tWRHW8 TBD TBD TBD ns ns ns WR Data setup timing Data hold timing tDS8 tDH8 TBD TBD ns ns D0 ∼ D 15 (VDD=2.4 ∼2.7V, Ta=-30∼+85°C) ITEM SYMBOL CONDITION MIN. MAX. UNIT PORT Address hold timing Address setup timing tAH8 tAS8 TBD TBD ns ns CS RS System cycle timing Write ”L” pulse width Write ”H” pulse width tCYC8 tWRLW8 tWRHW8 TBD TBD TBD ns ns ns WR Data setup timing Data hold timing tDS8 tDH8 TBD TBD ns ns D0 ∼ D 15 (VDD=1.7 ∼2.4V, Ta=-30∼+85°C) ITEM SYMBOL CONDITION MIN. MAX. UNIT PORT Address hold timing Address setup timing tAH8 tAS8 TBD TBD ns ns CS RS System cycle timing Write ”L” pulse width Write ”H” pulse width tCYC8 tWRLW8 tWRHW8 TBD TBD TBD ns ns ns WR Data setup timing Data hold timing tDS8 tDH8 TBD TBD ns ns D0 ∼ D 15 notice) All timing reference is 20% and 80% of VDD and 80%. tCYC8 tAS8 CS WR RS D0 ∼ D 15 tAH8 tWRLW8 tWRHW8 tDS8 tDH8 |
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