 |
Moteur de recherche de fiches techniques de composants électroniques |
|
|
Moteur de recherche de fiches techniques de composants électroniques |
|
HDMP-1012 Fiches technique(PDF) 27 Page - Agilent(Hewlett-Packard) |
|
|
|||||||||||||||||||||||||||||
HDMP-1012 Fiches technique(HTML) 27 Page - Agilent(Hewlett-Packard) |
|
|
27 / 42 page  599 HDMP-1014 (Rx) Detectable Error States M20SEL Not Asserted (16 bit mode) D-Field C-Field xxxxxxx xx xxxxxxx x00x xxxxxxx xx xxxxxxx x11x xxxxxxx 0x xxxxxxx 1100 xxxxxxx 11 xxxxxxx 1100 xxxxxxx xx xxxxxxx 1010 xxxxxxx xx xxxxxxx 0101 HDMP-1014 (Rx) Detectable Error States M20SEL Asserted (20 bit mode) D-Field C-Field xxxxxxxxx xx xxxxxxxxx x00x xxxxxxxxx xx xxxxxxxxx x11x xxxxxxxxx 0x xxxxxxxxx 1100 xxxxxxxxx 11 xxxxxxxxx 1100 xxxxxxxxx xx xxxxxxxxx 1010 xxxxxxxxx xx xxxxxxxxx 0101 Tx Operation Principles The HDMP-1012 (Tx) is imple- mented in a high performance silicon bipolar process. The Tx performs the following functions for link operation: • Phase lock to frame rate clock • Clock multiplication • Frame encoding • Multiplexing In normal operation, the Tx phase locks to a user supplied frame rate clock and multiplies the frequency to produce the high speed serial clock. When locked, the Tx indicates that it is locked by asserting the LOCKED output. When the ED input is asserted, the Tx asserts the RFD signal indicating that it is now ready to transmit data or control frames. The Tx can accept either 16 or 17 bit wide parallel data and produce a 20 bit frame. It also can accept 20 or 21 bit data and produce a 24 bit frame. Similarly, either 14 bit or 18 bit control words can be transmitted in a 20 bit or 24 bit frame respectively. Tx Encoding A simplified block diagram of the transmitter is shown in Figure 4. The PLL/Clock Generator locks onto the incoming frame rate (or one-half frame rate) clock and multiplies it up to the serial clock rate. It also generates all the internal clock signals required by the Tx chip. The data inputs, D0-D19, as well as the control signals; ED, FF, DAV*, CAV*, and FLAG are latched in on the rising edge of an internally generated frame rate clock. The data field is then encoded depending on the state of the control signals. At the same time, the coding field is generated. At this point, the entire frame has been constructed in parallel form and its sign is determined. This frame sign is compared with the accumulated sign of previously transmitted bits to decide whether to invert the frame. If the sign of the current frame is the same as the sign of the previously transmitted bits, then the frame is inverted. If the signs are opposite, the frame is not inverted. No inversion is |
|
Lien URL |
| ALLDATASHEET vous a-t-il été utile ? [ DONATE ] |
À propos de Alldatasheet | Publicité | Contactez-nous | Politique de confidentialité | Lien vers la fiche technique | Echange de liens | Fabricants All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
French ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
