HDMP-1012 datasheet(21/42 Pages) HP

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593

Rx I/O Definition (cont’d.)

Name

Type

Signal

LIN LIN*

I-H50

Loop Back Serial Data Input: Use this input when LOOPEN is

active. Unlike the DIN, DIN* inputs, this input does not have a cable

equalizer. In normal usage, this input will be connected to the Tx

chip LOUT, LOUT* outputs. This allows the user to check the

near-end functionality of the Tx and Rx pair independent of the

transmission medium

LOOPEN

I-ECL

Loop Back Control: When asserted, this signal causes the loop back

data inputs LIN, LIN* to be used instead of the normal data inputs

DIN, DIN*.

LINKRDY*

O-ECL

Link Ready Indicator: This active-low output is a retimed version

of the ACTIVE input. ACTIVE is normally driven by the Rx state

machine output. LINKRDY* then indicates that the startup sequence

is complete and that the data and control indications are valid.

M20SEL

I-ECL

16 or 20 Bit Word Select: When this signal is high, the link operates

in 20 Bit data reception mode. Otherwise, the link operates in 16 Bit

mode and data outputs D16-D19 are undefined.

NCLK

O-ECL

Nibble Clock Monitor: Leave unterminated in normal use.

TEMP

Temperature Sense Diode: Used during wafer and package test

only. It should be left open.

PH1

O-ECL

Phase Detector Test Output: The output from the phase/frequency

detector in the Rx PLL. When PH1 is high, the VCO should increase

frequency. When low, the VCO should decrease frequency.

SMRST0*

I-ECL

State Machine Reset Inputs: Each of these active-low input pins

SMRST1*

reset the Rx state machine to the initial start-up state. This initiates

a complete PLL restart and handshake at both ends of the duplex

link. Normally, SMCRST0* is connected to a power-up reset circuit

or a host system reset signal. The SMCRST1* input is normally

connected to the Tx LOCKED output. The LOCKED signal holds the

state-machine in the start-up state until the Tx PLL is locked.

STAT0

O-ECL

State Machine Status Outputs: These outputs indicate the current

STAT1

state-machine state. They are used to directly control the Tx ED,

Tx FF, Rx FDIS, and Rx ACTIVE lines.

STRBOUT

O-ECL

Recovered Frame-rate Data Clock Output: This output is the PLL

recovered frame rate clock. D0-D19, FLAG, DAV, CAV, FF, LINKRDY,

and ERROR should all be latched on the rising edge of STRBOUT.

TCLK

I-H50

External VCO Replacement Test Clock: When TCLKSEL in

TCLK*

enabled, this input is used in place of the normal VCO signal,

effectively disabling the PLL and allowing the user to provide an

external retiming clock for testing.

TCLKSEL

I-ECL

Enable Test Clock Input: When this input is active, the TCLK,

TCLK* inputs are used in place of the normal VCO signal. This

feature is useful both for synchronous systems and for chip testing.

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