B13 datasheet(8/14 Pages) MICREL

8 / 14 page

Micrel, Inc.

SM803020

July 22, 2013

Revision 1.0

hbwhelp@micrel.com or (408) 955-1690

AC Electrical Characteristics

VDD = VDDO1/2 = 3.3V ±5% or 2.5V ±5%

VDD = 3.3V ±5%, VDDO1/2 = 3.3V ±5% or 2.5V ±5%

TA = −40°C to +85°C

Symbol

Parameter

Condition

Min.

Typ.

Max.

Units

FIN

Input Frequency

39.0625

MHz

FOUT

Output Frequency

LVPECL, LVDS, HCSL, LVCMOS

156.25

MHz

TR/TF

Output Rise/Fall Time

20% – 80%

LVPECL output

135

350

LVDS output

140

300

HCSL output

175

340

700

LVCMOS output

100

200

400

ODC

Output Duty Cycle

Tpd

Input to Output Propagation Delay

ZDB mode

−

100

Synthesizer/Bypass mode

TSKEW

Output-to-Output Skew(4)

Note 5, same output bank

TLOCK

PLL Lock Time

Tjit(∅)

RMS Phase Jitter(6)

Integration range (12kHz to 20MHz)

180

Notes:

4. Defined as skew between outputs at the same supply voltage and with equal load conditions; measured at the output differential crossing points.

5. Output-to-output skew is only defined for outputs in the same PLL bank [A:B, C:D] with the same output type setting.

6. All phase noise measurements were taken with an Agilent 5052B phase noise system.

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