PI3VDP411LSA datasheet(8/13 Pages) PERICOM

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PS9059A

07/28/12

PI3VDP411LSA

Dual Mode DisplayPort™ to DVI/HDMI™ Electrical bridge (Level Shifter)

Table: Differential Input Characteristics forIN_Dx signals

Symbol

Parameter

Min Typ Max Units

Comments

Tbit

UI, Unit Interval

360

Tbit is determined by the display mode. Nominal

bit rate ranges from 250Mbps to 2.5Gbps per lane.

Nominal Tbit at 2.5 Gbps = 400 ps. 360ps = 400ps-

10%

VRX_DIFF

Input Differential Volt-

age Level

0.175

1.200 V

See note 1 below

TRX_EYE

Minimum Eye Width at

IN_D input pair

0.8

Tbit

VCM-ACp-p

AC Peak Common

Mode Input Voltage

100

See note 2 below

ZRX_DC

Required IN_D+ as well as IN_D- DC impedance

(50 ±20% tolerance).

ZRX-Bias

2.0

Intended to limit power-up stress on chipset's PCIE

output buffers.

ZRX_HIGH-Z

100

k Ω

Differential inputs must be in a high impedance

state when OE# is HIGH.

1. VRX-DIFF = 2x|VRX-D- -VRX-D-| Applies to IN_Dx signals

2. VCM-AC-p-p = |VRX-D- - VRX-D-|/2 - VRX-CM-DC

VRX-CM-DC = DC(avg) of |VRX-D+ + VRX-D-|/2

VCM-AC-p-p includes all frequencies above 30 kHz.

TMDS Outputs

The level shifter's TMDS outputs are required to meet HDMI 1.3 specifications.

The HDMI 1.3 Specification is assumed to be the correct reference in instances where this document conflicts with the HDMI 1.3

specification.

12-0236

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