Pad No.

Pad Name

X

Y

Pad No.

Pad Name

X

Y

20

SEG20

1970

995

53

INT

70

1340

21

SEG21

1970

1110

54

IOM1

70

1225

22

SEG22

1970

1225

55

IOM2

70

1110

23

SEG23

1970

1340

56

IOM3

70

995

24

SEG24

1970

1455

57

IOM4

70

880

25

SEG25

1970

1570

58

VDD1

70

765

26

SEG26

1970

1685

59

VDD2

70

650

27

SEG27

1970

1800

60

VDD3

70

535

28

SEG28

1970

1915

61

CUP1

70

420

29

SEG29

1970

2045

62

CUP2

70

290

30

SEG30

1970

2175

63

COM1

70

160

31

SEG31

1840

2265

64

COM2

200

70

32

SEG32

1710

2265

65

COM3

330

70

33

SEG33

1595

2265

66

COM4

445

70

Chip size: 84.65 x 96.45 mil

2

Pad Descriptions

Pad Name

I/O

Description

BAK

Positive back-up voltage.

In Li mode, connects a 0.1u capacitance to GND.

VDD1

VDD2

VDD3

LCD drives the voltage and positive supply voltage.

RESET

I

Input pin from LSI reset request signal.

Internal pull-down resistor.

INT

I

Input pin for external INT request signal.

Falling or rising edge triggered by mask option.

Internal pull-down or pull-up resistor or none is selected by mask option.

TESTA

I

Test signal input pin.

CUP1

CUP2

O

Switching pins for supplying the LCD driving voltage to the VDD1, 2, 3 pins.

Connects the CUP1 and CUP2 pins with nonpolarized electrolytic capacitor if

1/2 or 1/3 bias mode has been selected.

In the static mode, these pins should be open.

XIN

XOUT

I

O

Time-based counter frequency (clock-specified, LCD alternating frequency,

alarm signal frequency) or system clock oscillation. 32kHz crystal oscillator.

Oscillation stops at the execution of STOP instruction.

CFIN

CFOUT

I

O

System clock oscillation.

Connected with ceramic resonator.

Connected with RC oscillation circuit.

Oscillation stops at the execution of STOP or SLOW instruction.

COM1~4

O

Output pins for supplying voltage to drive the common pins of the LCD or LED

panel.

SEG1~42

O

Output pins for LCD or LED panel segment.

IOA1~4

I/O

Input/Output port A can use software to define the internal pull-low resistor and

chattering clock in order to reduce input bounce and generate interrupt.

This port shares pins with SEG37~40 and is set by mask option.

This port also shares pins with CC, RR, RT and RH, and is set by mask option.

Preliminary

4

Ver. 0.0

APU428