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STM8S003K3 Fiches technique(PDF) 50 Page - STMicroelectronics |
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STM8S003K3 Fiches technique(HTML) 50 Page - STMicroelectronics |
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50 / 100 page ![]() Figure 9: fCPUmax versus VDD 16 12 8 4 0 2.95 4.0 5.0 5.5 f CPU (MHz) Functionality guaranteed @TA-40 to 85 °C Supply voltage Functionality not guaranteed in this area Table 19: Operating conditions at power-up/power-down Unit Max Typ Min Conditions Parameter Symbol μs/V ∞ 2 VDD rise time rate tVDD ∞ 2 VDD fall time rate (1) ms 1.7 VDD rising Reset release delay tTEMP V 2.85 2.7 2.6 Power-on reset threshold VIT+ 2.8 2.65 2.5 Brown-out reset threshold VIT- mV 70 Brown-out reset hysteresis VHYS(BOR) (1) Reset is always generated after a t TEMP delay. The application must ensure that VDD is still above the minimum ooperating voltage (VDD min) when the tTEMP delay has elapsed. VCAP external capacitor 9.3.1 Stabilization for the main regulator is achieved connecting an external capacitor CEXT to the VCAP pin. CEXT is specified in the Operating conditions section. Care should be taken to limit the series inductance to less than 15 nH. Figure 10: External capacitor CEXT C Rleak ESR ESL 1. ESR is the equivalent series resistance and ESL is the equivalent inductance. DocID018576 Rev 3 50/100 STM8S003K3 STM8S003F3 Electrical characteristics |
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