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STM8S003K3 Fiches technique(PDF) 31 Page - STMicroelectronics |
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STM8S003K3 Fiches technique(HTML) 31 Page - STMicroelectronics |
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31 / 100 page ![]() Reset status Register name Register label Block Address 0x00 I 2C Clock control register high I2C_CCRH 0x00 521C 0x02 I 2C TRISE register I2C_TRISER 0x00 521D 0x00 I 2C packet error checking register I2C_PECR 0x00 521E Reserved area (17 bytes) 0x00 521F to 0x00 522F 0xC0 UART1 status register UART1_SR UART1 0x00 5230 0xXX UART1 data register UART1_DR 0x00 5231 0x00 UART1 baud rate register 1 UART1_BRR1 0x00 5232 0x00 UART1 baud rate register 2 UART1_BRR2 0x00 5233 0x00 UART1 control register 1 UART1_CR1 0x00 5234 0x00 UART1 control register 2 UART1_CR2 0x00 5235 0x00 UART1 control register 3 UART1_CR3 0x00 5236 0x00 UART1 control register 4 UART1_CR4 0x00 5237 0x00 UART1 control register 5 UART1_CR5 0x00 5238 0x00 UART1 guard time register UART1_GTR 0x00 5239 0x00 UART1 prescaler register UART1_PSCR 0x00 523A Reserved area (21 bytes) 0x00 523B to 0x00 523F 0x00 TIM1 control register 1 TIM1_CR1 TIM1 0x00 5250 0x00 TIM1 control register 2 TIM1_CR2 0x00 5251 31/100 DocID018576 Rev 3 Memory and register map STM8S003K3 STM8S003F3 |
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