L6470PD datasheet(32/70 Pages) STMICROELECTRONICS

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Functional description

L6470

32/70

Doc ID16737 Rev 5

Figure 14.

Internal 3 V linear regulator

6.17

BUSY\SYNC pin

This pin is an open drain output which can be used as the busy flag or synchronization

signal according to the SYNC_EN bit value (STEP_MODE register).

6.17.1

BUSY operation mode

The pin works as busy signal when the SYNC_EN bit is set low (default condition). In this

mode the output is forced low while a constant speed, absolute positioning or motion

command is under execution. The BUSY pin is released when the command has been

executed (target speed or target position reached). The STATUS register includes a BUSY

flag that is the BUSY pin mirror (see Section 9.1.22).

In the case of daisy chain configuration, BUSY pins of different ICs can be hard-wired to

save host controller GPIOs.

6.17.2

SYNC operation mode

The pin works as synchronization signal when the SYNC_EN bit is set high. In this mode a

step-clock signal is provided on the output according to a SYNC_SEL and STEP_SEL

parameter combination (see Section 9.1.19).

VREG

VDD

VSA

VSB

AGND

DGND

VDD

μC

VREG

VDD

VSA

VSB

AGND

DGND

3.3V

REG.

VBAT

Logig supplied by

INTERNAL voltage regulator

Logig supplied by

EXTERNAL voltage regulator

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