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CS1630 Fiches technique(PDF) 38 Page - Cirrus Logic |
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CS1630 Fiches technique(HTML) 38 Page - Cirrus Logic |
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38 / 56 page ![]() CS1630/31 38 DS954F2 6.22 Configuration 17 (Config17) – Address 49 6.23 Configuration 18 (Config18) – Address 50 7 654 32 10 DITHER RESYNC T2CH2GAIN5 T2CH2GAIN4 T2CH2GAIN3 T2CH2GAIN2 T2CH2GAIN1 T2CH2GAIN0 Number Name Description [7] DITHER Configures dither on the second stage primary side peak current threshold. 0 = Disable dither 1 = Enable dither [6] RESYNC Configures resynchronization of a dual channel second stage design where the channel synchronization circuit is not directly driven from the SYNC pin. Bit RESYNC controls the behavior of bits EXIT_PH[3:0] and DECL_PH[3:0] (see "Configuration 15 (Config15) – Address 47" on page 37). 0 = Disable phase resynchronization 1 = Enable phase resynchronization [3:0] T2CH2GAIN[5:0] Sets T2 compensation gain T2CH2CompGain for channel 2 which is required when T2 measurement compensation is enabled for flyback designs. The value is an unsigned integer in the range of 0 T2CH2CompGain<63. Compen- sated T2 time T2Compensated used in the second stage charge regulation loop is given by: where, T2CH2CompGain is a decimal number the range of 0.0T2CH2CompGain<4.0. 7 654 32 10 LEB3 LEB2 LEB1 LEB0 TEB3 TEB2 TEB1 TEB0 Number Name Description [7:4] LEB [3:0] Configures the leading-edge blanking time TLEB for the second stage peak current measurement. The output of the current sense comparator which con- trols the primary side peak current is ignored for time TLEB from the rising edge of the gate drive signal. [3:0] TEB[3:0] Configures the trailing-edge blanking time TTEB for zero-current detection. The ZCD comparator output signal used to detect the secondary side inductor demagnetization is blanked for time TTEB after the falling edge of the second stage gate drive signal. T2Compensated T2 = Measured TZCD Ri gEdge sin T2CH2CompGain – T2CH2CompGain T2CH2GAIN[5:0] 0.0625 = TLEB LEB[3:0] = 250ns TTEB TEB[3:0] = 2 50ns |
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