41594B datasheet(87/372 Pages) MICROCHIP

87 / 372 page

 2011-2012 Microchip Technology Inc.

Preliminary

DS41594B-page 87

PIC12LF1840T48A

8.5.5

PIR2 REGISTER

The PIR2 register contains the interrupt flag bits, as

shown in Register 8-5.

Note:

Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of

its corresponding enable bit or the Global

Enable bit, GIE, of the INTCON register.

User

software

should

ensure

the

appropriate interrupt flag bits are clear prior

to enabling an interrupt.

PIR2: PERIPHERAL INTERRUPT REQUEST REGISTER 2

R/W-0/0

U-0

R/W-0/0

U-0

OSFIF

—

C1IF

EEIF

BCL1IF

—

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

u = Bit is unchanged

x = Bit is unknown

-n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set

‘0’ = Bit is cleared

bit 7

OSFIF: Oscillator Fail Interrupt Flag bit

1 = Interrupt is pending

0 = Interrupt is not pending

bit 6

Unimplemented: Read as ‘0’

bit 5

C1IF: Comparator C1 Interrupt Flag bit

1 = Interrupt is pending

0 = Interrupt is not pending

bit 4

EEIF: EEPROM Write Completion Interrupt Flag bit

1 = Interrupt is pending

0 = Interrupt is not pending

bit 3

BCL1IF: MSSP Bus Collision Interrupt Flag bit

1 = Interrupt is pending

0 = Interrupt is not pending

bit 2-0

Unimplemented: Read as ‘0’

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